1. Technical Field
The inventive concept relates to a semiconductor device and a method of fabricating the same, and more particularly, to technology to improve gate-induced drain leakage (GIDL) of a buried gate and to improve device characteristic and reliability with reduction in a gate resistance.
2. Related Art
In recent years, although demands on large capacity of dynamic random access memories (DRAMs) have been increasing, there is a limit to increase in the capacity of the DRAMs due to increased chip size. With the increase of the chip size, the number of chips per a wafer is reduced and yield of the device is reduced. Therefore, in recent years, there are studies to reduce a cell area through change of a cell layout and thus to integrate as many memory cells as possible on one wafer.
According to this, buried gate structures have been developed. In the buried gate, leakage current due to gate induced drain leakage (GIDL) of a semiconductor device, is increased between a conductive material (gate electrode) and an N type junction of an active region, or between the conductive material and a storage node contact. Refresh time (tREF) of the whole semiconductor device may be reduced due to degradation of GIDL.
To prevent the leakage current from being increased due to GIDL, a conductive material (gate electrode) of the buried gate is overetched to minimize an overlapping area between the storage node contact and the conductive material (gate electrode).
However, although the conductive material (gate electrode) of the buried gate is over etched to prevent the leakage current from being increased due to GIDL, resistance of the buried gate may be increased to degrade operation speed, current drivability, and a write-recovery time (tWR) in the semiconductor device.